3bit counter verilog

module counter(
 output [2:0] out,
 input clk, rst);
 wire [2:0] ns;
 counter_code code(ns, out);
 dff DFF[2:0](out, ns, clk, rst); 
endmodule

// 7,1,6,2,5,3,4,0  start over
module counter_code(
   output [2:0] next,
   input [2:0] c);   
   wire [2:0]c_n;   
   not cnot[2:0] (c_n, c);

   // this is where your logic goes for the counter steps
   and(n0mid1,c_n[2],c_n[1],c_n[0]);
   and(n0mid2,c[2],c[1],c[0]);
   and(n0mid3,c_n[2],c[1],c_n[0]);   
   and(n0mid4,c[2],c_n[1],c[0]);
   
   or(next[0],n0mid1,n0mid2,n0mid3,n0mid4);   
   
   nor(n1mid1,c[2],c[1]);
   and(n1mid2,c[2],c_n[1],c[0]);
   and(n1mid3,c[2],c[1],c_n[0]);
   
   or(next[1],n1mid1,n1mid2,n1mid3);   
   
   not(next[2] ,c[2]);  
endmodule