Tuesday, September 25, 2007

Structural 16bit CLA adder in Verilog

A whole 16 bit adder

module pfa(
output p, g, s,
input a, b, cin);
xor #1 sumer(s, a, b, cin);
xor #1 proper(p, a, b);
and #1 gener(g, a, b);

//cla module 4 bit
module cla(
output p_up, g_up,
output [3:0] cout, // assumed [3:1] was typo becuase it made design less elegant
input [3:0] p, g,
input cin);

//assign p_up = &(p);
and #1 (p_up, p);
wire p3g2, p3p2g1, p3p2p1g0, p3p2p1p0cin;

and #1(p3g2,p[3],g[2]);
and #1(p3p2g1,p[3],p[2],g[1]);
and #1(p3p2p1g0,p[3],p[2],p[1],g[0]);

and #1(p3p2p1p0cin,p[3],p[2],p[1],p[0],cin);

//assign g_up = g[3] | p[3]&g[2] | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0];
or #1 (g_up,g[3],p3g2,p3p2g1,p3p2p1g0);

//assign cout[3] = g[3] | p[3]&g[2] | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0] | p[3]&p[2]&p[1]&p[0]&cin;
or #1(cout[3],g[3],p3g2,p3p2g1,p3p2p1g0,p3p2p1p0cin);

wire p2g1,p2p1g0,p2p1p0cin,p1g0,p1p0cin,p0cin;

and #1(p2g1,p[2],g[1]);
and #1(p2p1g0,p[2],p[1],g[0]);
and #1(p2p1p0cin,p[2],p[1],p[0],cin);
and #1(p1g0,p[1],g[0]);
and #1(p1p0cin,p[1],p[0],cin);
and #1(p0cin,p[0],cin);

//assign cout[2] = g[2] | p[2]&g[1] | p[2]&p[1]&g[0] | p[2]&p[1]&p[0]&cin;
or #1(cout[2], g[2],p2g1,p2p1g0,p2p1p0cin);

//assign cout[1] = g[1] | p[1]&g[0] | p[1]&p[0]&cin;
or #1(cout[1],g[1],p1g0,p1p0cin);

//assign cout[0] = g[0] | p[0]&cin;
or #1(cout[0],g[0],p0cin);

//put the cla and #1 adders together to make them easier to merge
module adder4_cla(
output co,
output [3:0] s,
output p_up,g_up,
input [3:0] a,b,
input cin);

wire [3:0] p,g;
wire [3:0] carry;

pfa add[3:0](.p(p),.g(g),.s(s),.a(a),.b(b),.cin({carry[2:0], cin}));

cla localcla(.p_up(p_up),.g_up(g_up),.cout(carry),.p(p),.g(g),.cin(cin));

assign co = carry[3];

module add16(
output co,
output [15:0] s,
input [15:0] a,b,
input cin);

wire [3:0] carry, p, g;
wire p_up, g_up;

wire c1,c2,c3,c4;

adder4_cla add1 (.co(c1),.s(s[3:0]),.p_up(p[0]),.g_up(g[0]),.a(a[3:0]),.b(b[3:0]),.cin(cin));
adder4_cla add2 (.co(c2),.s(s[7:4]),.p_up(p[1]),.g_up(g[1]),.a(a[7:4]),.b(b[7:4]),.cin(carry[0]));
adder4_cla add3 (.co(c3),.s(s[11:8]),.p_up(p[2]),.g_up(g[2]),.a(a[11:8]),.b(b[11:8]),.cin(carry[1]));
adder4_cla add4 (.co(c4),.s(s[15:12]),.p_up(p[3]),.g_up(g[3]),.a(a[15:12]),.b(b[15:12]),.cin(carry[2]));

cla finalcla(.p_up(p_up),.g_up(g_up),.cout(carry),.p(p),.g(g),.cin(cin));

assign co = carry[3];

1 comment:

raju said...

Respected sir ,

Sir ,I Ashok from karanataka studying engg sir i am doing one project on verilog that is 16 bit vedic multiplier sir i want veriolg code for this sir , pls send the code to my mail sir:- ashok_laki@rediffmail.com