Structural CLA verilog 4bit module with expanded terms

Carry Look Ahead adders are amazing, unfortunately they are a pain to design... here is a module I use quite often.

//cla module 4 bit
module cla(
   output   p_up, g_up,
   output [3:0]  cout,  // assumed [3:1] was typo becuase it made design less elegant
   input  [3:0]  p, g,
   input cin);
 
   //assign p_up = &(p);
   and #1 (p_up, p);
   wire p3g2, p3p2g1, p3p2p1g0, p3p2p1p0cin;
   
   and #1(p3g2,p[3],g[2]);
   and #1(p3p2g1,p[3],p[2],g[1]);
   and #1(p3p2p1g0,p[3],p[2],p[1],g[0]);
   
   and #1(p3p2p1p0cin,p[3],p[2],p[1],p[0],cin);
   
   //assign g_up = g[3] | p[3]&g[2] | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0];
   or #1 (g_up,g[3],p3g2,p3p2g1,p3p2p1g0);
   
   //assign cout[3] = g[3] | p[3]&g[2] | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0] | p[3]&p[2]&p[1]&p[0]&cin;
   or #1(cout[3],g[3],p3g2,p3p2g1,p3p2p1g0,p3p2p1p0cin);
   
   wire p2g1,p2p1g0,p2p1p0cin,p1g0,p1p0cin,p0cin;
   
   and #1(p2g1,p[2],g[1]);
   and #1(p2p1g0,p[2],p[1],g[0]);
   and #1(p2p1p0cin,p[2],p[1],p[0],cin);
   and #1(p1g0,p[1],g[0]);
   and #1(p1p0cin,p[1],p[0],cin);
   and #1(p0cin,p[0],cin);
   
   //assign cout[2] = g[2] | p[2]&g[1] | p[2]&p[1]&g[0] | p[2]&p[1]&p[0]&cin;
   or #1(cout[2], g[2],p2g1,p2p1g0,p2p1p0cin);
   
   //assign cout[1] = g[1] | p[1]&g[0] | p[1]&p[0]&cin;
   or #1(cout[1],g[1],p1g0,p1p0cin);
   
   //assign cout[0] = g[0] | p[0]&cin;
   or  #1(cout[0],g[0],p0cin);
endmodule