module decoder3_8(
output [7:0] out,
input [2:0] sel);
assign out = ( sel == 3'b000) ? 8'b1111_1110 :
( sel == 3'b001) ? 8'b1111_1101 :
( sel == 3'b010) ? 8'b1111_1011 :
( sel == 3'b011) ? 8'b1111_0111 :
( sel == 3'b100) ? 8'b1110_1111 :
( sel == 3'b101) ? 8'b1101_1111 :
( sel == 3'b110) ? 8'b1011_1111 :
( sel == 3'b111) ? 8'b0111_1111 :
8'b1111_1111;
endmodule
module demux1_8 (
output[7:0] sig_out,
input[2:0] sel,
input sig_in);
wire[7:0] selout;
decoder3_8 selector(selout, sel);
or finalor[7:0](sig_out, selout, sig_in);
endmodule
Tuesday, September 25, 2007
Verilog 3 to 8 decoder and 1 to 8 demux RTL
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