16bit register file: 2 read & 2 write ports

This is a beautiful piece of code :-)

module reg_file(output [15:0] read1data, read2data, input [15:0] write1data, write2data, input [2:0] read1regsel, read2regsel, write1regsel, write2regsel, input clk, rst, write1, write2);
    wire [7:0] reg_final_write, reg1_write, reg2_write;
    wire [127:0] write_final_data;
    wire [127:0] regfileout;
    mux16b_8_1 muxAB [1:0] ({read1data, read2data}, {read1regsel, read2regsel}, {regfileout, regfileout}); //select 2 registers to read
    
    decoder_3_to_8 decoder(reg1_write, write1regsel, write1);   //select which register to write to
    decoder_3_to_8 decoder2(reg2_write, write2regsel, write2);   //select which register to write to
    mux16b_2_1 writeportselector [7:0] (write_final_data, reg2_write, write1data, write2data);
    
    assign reg_final_write = reg1_write | reg2_write;
    
    reg16bit reg_16wide [7:0] (regfileout, write_final_data, clk, rst, reg_final_write);   //registers    
endmodule

//sel = 0 out = a
module mux16b_2_1(output [15:0] out, input sel, input [15:0] a, b);
  assign out = (sel) ? b : a;
endmodule

module mux16b_8_1(output [15:0] out, input [2:0] sel, input [127:0] in);
  assign out = 
  (sel == 3'b000) ? in[15:0]:
  (sel == 3'b001) ? in[31:16]:
  (sel == 3'b010) ? in[47:32]:
  (sel == 3'b011) ? in[63:48]:
  (sel == 3'b100) ? in[79:64]:
  (sel == 3'b101) ? in[95:80]:
  (sel == 3'b110) ? in[111:96]: in[127:112];
endmodule

module decoder_3_to_8(output [7:0] out, input [2:0] in, input en);
  assign out =(en == 1'b0) ? 8'd0:
  (in == 3'b000) ? 8'd1:
  (in == 3'b001) ? 8'd2:
  (in == 3'b010) ? 8'd4:
  (in == 3'b011) ? 8'd8:
  (in == 3'b100) ? 8'd16:
  (in == 3'b101) ? 8'd32:
  (in == 3'b110) ? 8'd64: 8'd128;
endmodule

module reg16bit(output [15:0] dataout, input [15:0] datain, input clk, rst, en);
  wire [15:0] regin;
  assign regin = en ? datain: dataout;
  dff dff_array [15:0](dataout, regin, clk, rst);
endmodule