7bit UART TX Transmitter

module uart_tx (output sd, output busy, input [6:0] data, input wr, rst, clk);
  reg [3:0] state, next_state;
  reg [9:0] shifter;

  parameter S_IDLE = 4'd0, S_BIT_START = 4'd1, S_BIT_P = 4'd9, S_BIT_STOP = 4'd10;

// continuous assignments
  assign busy = (state != S_IDLE);
  assign sd = shifter[0];

// synchronous behavior(s)
always @ (posedge clk) begin   
 if(rst) begin
  state <= S_IDLE;
  shifter <= 10'b11_1111_1111;
 end
 else begin
  state <= next_state;   // update state
  if(wr)     // load new frame
   shifter <= {1'b1, ~(^(data)), data, 1'b0}; // could leave stop bit off!
  else     // shift current frame
   shifter <= {1'b1, shifter[9:1]}; // shift in idle channel
 end
end
// next state logic
always @ (state, wr) begin
 case (state)
 S_IDLE:
  if(wr) next_state = S_BIT_START;
  else next_state = S_IDLE;
 S_BIT_STOP:
  next_state = S_IDLE;
 default:
  next_state = state + 4'd1;
 endcase
end

endmodule